Describe the L1 instruction and data caches in the CPU nodes:
- The L1 caches for the Cortex-A15 CPU cores are organized as 16 KiB x
2 ways.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
arch/arm/boot/dts/r8a7791.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 8013223448b5b464..4e4011a2978bcfce 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -52,6 +52,16 @@
clocks = <&cpg_clocks R8A7791_CLK_Z>;
clock-latency = <300000>; /* 300 us */
+ i-cache-size = <0x8000>;
+ i-cache-sets = <512>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <512>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2_CA15>;
+
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
<1312500 1000000>,
@@ -66,6 +76,16 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
+
+ i-cache-size = <0x8000>;
+ i-cache-sets = <512>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <512>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2_CA15>;
};
};
--
1.9.1
--
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