On 20 May 2015 at 02:34, Brian Norris <computersforpeace@xxxxxxxxx> wrote: > On Sun, May 17, 2015 at 05:41:04PM +0200, Hauke Mehrtens wrote: >> This driver registers at the bcma bus and drives the NAND core if it >> was found on this bus. The bcma bus with this NAND core is used on the >> bcm53xx and bcm47xx Northstar SoC with ARM CPU cores. The memory ranges >> are automatically detected by bcma and the irq numbers read from device >> tree by bcma bus driver. > > If you're going to use device tree for part of it (IRQs) why not the > whole thing? > >> This is based on the iproc driver. > > This looks like you could probably get by with just using iproc_nand.c > as-is. The main NAND core is apparently MMIO-accessible on your chips, > so aren't the BCMA bits you're touching also? That's right, in case of SoCs cores are MMIO-accessible, however I see few reasons for writing this driver as bcma based: 1) MMIO access isn't available for bcma bus /hosted/ on PCIe devices. By using bcma layer we write generic drivers. 2) bcma detects cores and their MMIO addresses automatically, if we are a bit lazy, it's easier to use it rather than keep hardcoding all addresses 3) There are some dependencies in cores initialization, e.g. ChipCommon core usually has to be initialized first 4) bcma provides some helpers like bcma_core_enable so we don't have to duplicate it in driver code That said, I'm for using bcma layer, even if there is some small DT involvement already. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
