This adds the NAND flash chip description for a standard chip found
connected to this SoC. The IRQ is fetched from the device tree
definition of the axi bus for this core and the memory ranges are
automatically probed.
Signed-off-by: Hauke Mehrtens <hauke@xxxxxxxxxx>
---
arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 12 +++++-------
arch/arm/boot/dts/bcm5301x.dtsi | 19 +++++++++++++++++++
2 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
index 946c728..0529682 100644
--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
@@ -25,13 +25,11 @@
axi@18000000 {
nand@28000 {
- reg = <0x00028000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x08000000>;
+ nandcs@0 {
+ partition@0 {
+ label = "ubi";
+ reg = <0x00000000 0x08000000>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 78aec62..1bccb59 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -142,5 +142,24 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ nand: nand@28000 {
+ reg = <0x00028000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcm,nand-has-wp;
+
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ };
+ };
};
};
--
2.1.4
--
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