Hi Geert-san,
Thank you for the review!
> Sent: Friday, May 15, 2015 12:48 AM
>
> Hi Shimoda-san,
>
> On Wed, May 13, 2015 at 11:27 AM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > Add binding document for Renesas PWM Timer on R-Car SoCs.
>
> Thanks for your patch!
>
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > ---
> > .../devicetree/bindings/pwm/renesas,pwm-rcar.txt | 21 +++++++++++++++++++++
> > 1 file changed, 21 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
> b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
> > new file mode 100644
> > index 0000000..38123f9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
> > @@ -0,0 +1,21 @@
> > +* Renesas R-Car PWM Timer Controller
> > +
> > +Required Properties:
> > +- compatible: must contain "renesas,pwm-rcar"
>
> Can you please add SoC-specific compatible values, too? That way we can handle
> SoC-specific differences if we ever encounter them.
> If I'm not mistaken, this PWM IP core is present on both R-Car Gen1 and Gen2
> SoCs?
According to the manuals of both R-Car Gen1 (H1, M1, E1) and Gen2,
this PWM IP core is present on them. Also this IP is present on R-Car next generation.
Of course, I can add SoC-specific compatible values, like "renesas,pwm-r7a7790" or
something. So, I will change the compatible values in v2 patch.
> > +- reg: base address and length of the registers block for the PWM
> > +- #pwm-cells: should be 7. See pwm.txt in this directory for a description of
> > + the cells format.
>
> Why 7? This is not the number of channels, cfr. pwm.txt you reference above:
>
> "pwm-specifier typically encodes the chip-relative PWM number and the PWM
> period in nanoseconds.
>
> Optionally, the pwm-specifier can encode a number of flags (defined in
> <dt-bindings/pwm/pwm.h>) in a third cell:
> - PWM_POLARITY_INVERTED: invert the PWM signal polarity"
>
> So 2 or 3 makes more sense to me.
Thank you very much for the point. I completely misunderstood this specification.
Since this PWM IP cannot control polarity, this value should be 2.
So, I will fix this in v2 patch.
Best regards,
Yoshihiro Shimoda
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