Hi Dmitry,
On Fri Mar 21, 2025 at 4:56 PM CET, Dmitry Baryshkov wrote:
> On Fri, Mar 21, 2025 at 03:45:01PM +0100, Luca Weiss wrote:
>> Add a node for the videocc found on the SM6350 SoC.
>>
>> Signed-off-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/qcom/sm6350.dtsi | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> index 00ad1d09a19558d9e2bc61f1a81a36d466adc88e..ab7118b4f8f8cea56a3957e9df67ee1cd74820a6 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> @@ -1952,6 +1952,20 @@ usb_1_dwc3_ss_out: endpoint {
>> };
>> };
>>
>> + videocc: clock-controller@aaf0000 {
>> + compatible = "qcom,sm6350-videocc";
>> + reg = <0 0x0aaf0000 0 0x10000>;
>
> 0x0, please.
There's currently 80 cases of 0 and 20 of 0x0 in this file, is 0x0
the preferred way nowadays?
If so, shall I also change 0 to 0x0 for reg in a separate patch?
Regards
Luca
>
>> + clocks = <&gcc GCC_VIDEO_AHB_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&sleep_clk>;
>> + clock-names = "iface",
>> + "bi_tcxo",
>> + "sleep_clk";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> cci0: cci@ac4a000 {
>> compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
>> reg = <0 0x0ac4a000 0 0x1000>;
>>
>> --
>> 2.49.0
>>
