On Sun, Mar 09, 2025 at 06:26:48PM +0100, Christian Marangi wrote: > Document support for Airoha AN8855 5-port Gigabit Switch. > > It does expose the 5 Internal PHYs on the MDIO bus and each port > can access the Switch register space by configurting the PHY page. nit: configuring > > Each internal PHY might require calibration with the fused EFUSE on > the switch exposed by the Airoha AN8855 SoC NVMEM. > > Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx> > --- > .../net/dsa/airoha,an8855-switch.yaml | 105 ++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > > diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > new file mode 100644 > index 000000000000..63bcbebd6a29 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Airoha AN8855 Gigabit Switch > + > +maintainers: > + - Christian Marangi <ansuelsmth@xxxxxxxxx> > + > +description: > > + Airoha AN8855 is a 5-port Gigabit Switch. > + > + It does expose the 5 Internal PHYs on the MDIO bus and each port > + can access the Switch register space by configurting the PHY page. Ditto. > + > + Each internal PHY might require calibration with the fused EFUSE on > + the switch exposed by the Airoha AN8855 SoC NVMEM. ...
