Hi Rasmus, On Wed, Mar 19, 2025 at 01:30:53PM +0100, Rasmus Villemoes wrote: > As the comments in ocelot-spi.c explain, after a chip reset, the > CFGSTAT register must be written again setting the appropriate number > of padding bytes; otherwise reads are not reliable. > > However, the way the code is currently structured violates that: After > the BIT_SOFT_CHIP_RST is written, ocelot_chip_reset() immediately > enters a readx_poll_timeout(). I ran this new version and everything worked - and I've not seen an issue in previous versions. I'm looking for guidance as to whether this should include a Fixes tag and be backported. Great find, by the way! Is there any information you would like from my setup? I'm happy to add a reviewed tag, and my "tested" would be that I ran it. Colin Foster
