The ocelot switches can also be strapped so that they can be
controlled via an MDIO bus (on either address 0 or 31). Mention that
and add an example.
Signed-off-by: Rasmus Villemoes <ravi@xxxxxxxxx>
---
.../devicetree/bindings/mfd/mscc,ocelot.yaml | 121 +++++++++++++++++-
1 file changed, 119 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
index 8bd1abfc44d99..bd2787a613e16 100644
--- a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
+++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
@@ -12,8 +12,8 @@ maintainers:
description: |
The Ocelot ethernet switch family contains chips that have an internal CPU
(VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
- the option to be controlled externally via external interfaces like SPI or
- PCIe.
+ the option to be controlled externally via external interfaces like SPI, MDIO
+ or PCIe.
The switch family is a multi-port networking switch that supports many
interfaces. Additionally, the device can perform pin control, MDIO buses, and
@@ -164,6 +164,123 @@ examples:
};
};
};
+ - |
+ #include <dt-bindings/phy/phy-ocelot-serdes.h>
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ soc@0 {
+ compatible = "mscc,vsc7512";
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mdio@7107009c {
+ compatible = "mscc,ocelot-miim";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7107009c 0x24>;
+
+ sw_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ sw_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+
+ mdio@710700c0 {
+ compatible = "mscc,ocelot-miim";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x710700c0 0x24>;
+ status = "disabled";
+ };
+
+ ocelot_gpio: pinctrl@71070034 {
+ compatible = "mscc,ocelot-pinctrl";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ocelot_gpio 0 0 22>;
+ reg = <0x71070034 0x6c>;
+ };
+
+ gpio@710700f8 {
+ compatible = "mscc,ocelot-sgpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x710700f8 0x100>;
+ status = "disabled";
+ };
+
+ ocelot_serdes: serdes@710d0000 {
+ compatible = "mscc,vsc7514-serdes";
+ reg = <0x710d0000 0x10000>;
+ #phy-cells = <2>;
+ };
+
+ ethernet-switch@71010000 {
+ compatible = "mscc,vsc7512-switch";
+ reg = <0x71010000 0x10000>,
+ <0x71030000 0x10000>,
+ <0x71080000 0x100>,
+ <0x710e0000 0x10000>,
+ <0x711e0000 0x100>,
+ <0x711f0000 0x100>,
+ <0x71200000 0x100>,
+ <0x71210000 0x100>,
+ <0x71220000 0x100>,
+ <0x71230000 0x100>,
+ <0x71240000 0x100>,
+ <0x71250000 0x100>,
+ <0x71260000 0x100>,
+ <0x71270000 0x100>,
+ <0x71280000 0x100>,
+ <0x71800000 0x80000>,
+ <0x71880000 0x10000>,
+ <0x71040000 0x10000>,
+ <0x71050000 0x10000>,
+ <0x71060000 0x10000>;
+ reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
+ "port2", "port3", "port4", "port5", "port6",
+ "port7", "port8", "port9", "port10", "qsys",
+ "ana", "s0", "s1", "s2";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ label = "swp1";
+ phy-handle = <&sw_phy1>;
+ phy-mode = "internal";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "swp2";
+ phy-handle = <&sw_phy2>;
+ phy-mode = "internal";
+ };
+
+ port@a {
+ reg = <10>;
+ label = "cpu";
+ ethernet = <&enetc_port0>;
+ phy-connection-type = "sgmii";
+ phys = <&ocelot_serdes 10 SERDES6G(2)>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+ };
...
--
2.49.0
