The SCP is currently described in the Devicetree as a single-core
processor, but really it is a cluster with two cores. Describe the full
cluster but enable only core0 on the current mt8188 platforms since
that's the only one usable with the upstream firmware.
Co-developed-by: Tinghan Shen <tinghan.shen@xxxxxxxxxxxx>
Signed-off-by: Tinghan Shen <tinghan.shen@xxxxxxxxxxxx>
Co-developed-by: Jason Chen <jason-ch.chen@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
Signed-off-by: Jason Chen <jason-ch.chen@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8188-evb.dts | 6 +++-
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 36 ++++++++++++++++------
.../boot/dts/mediatek/mt8390-genio-common.dtsi | 6 +++-
3 files changed, 37 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts b/arch/arm64/boot/dts/mediatek/mt8188-evb.dts
index f89835ac36f36f86e2054ae0c332172be97b049a..f4c207d65b877e1eefaa26540446c3c06369ca21 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8188-evb.dts
@@ -331,7 +331,11 @@ &pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
-&scp {
+&scp_cluster {
+ status = "okay";
+};
+
+&scp_c0 {
memory-region = <&scp_mem_reserved>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 4437b1820f2685281c3a373bf626f72b53503e62..bea3cee9b8e8f0dc656edd85e63f4f6f6645607f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1382,12 +1382,30 @@ gce1: mailbox@10330000 {
clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
};
- scp: scp@10500000 {
- compatible = "mediatek,mt8188-scp";
- reg = <0 0x10500000 0 0x100000>,
- <0 0x10720000 0 0xe0000>;
- reg-names = "sram", "cfg";
- interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ scp_cluster: scp@10720000 {
+ compatible = "mediatek,mt8188-scp-dual";
+ reg = <0 0x10720000 0 0xe0000>;
+ reg-names = "cfg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x10500000 0x100000>;
+ status = "disabled";
+
+ scp_c0: scp@0 {
+ compatible = "mediatek,scp-core";
+ reg = <0x0 0xd0000>;
+ reg-names = "sram";
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ scp_c1: scp@d0000 {
+ compatible = "mediatek,scp-core";
+ reg = <0xd0000 0x2f000>;
+ reg-names = "sram";
+ interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
};
afe: audio-controller@10b10000 {
@@ -2249,7 +2267,7 @@ dma-controller@14001000 {
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
<CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
- mediatek,scp = <&scp>;
+ mediatek,scp = <&scp_c0>;
};
display@14002000 {
@@ -2704,7 +2722,7 @@ video_decoder: video-decoder@18000000 {
iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>;
#address-cells = <2>;
#size-cells = <2>;
- mediatek,scp = <&scp>;
+ mediatek,scp = <&scp_c0>;
video-codec@10000 {
compatible = "mediatek,mtk-vcodec-lat";
@@ -2828,7 +2846,7 @@ video_encoder: video-encoder@1a020000 {
<&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>,
<&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>;
power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
- mediatek,scp = <&scp>;
+ mediatek,scp = <&scp_c0>;
};
jpeg_encoder: jpeg-encoder@1a030000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
index 60139e6dffd8e0e326690d922f3360d829ed026b..65952bcf5d03e3b22984dd3e997e7107e74dac72 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
@@ -1055,7 +1055,11 @@ power-key {
};
};
-&scp {
+&scp_cluster {
+ status = "okay";
+};
+
+&scp_c0 {
memory-region = <&scp_mem>;
status = "okay";
};
--
2.49.0
