On Fri, 14 Mar 2025 16:35:50 +0100, Nicolas Frattaroli wrote:
> The GPIO3 A4 pin on the ArmSoM Sige5 is routed to the 40-pin GPIO
> header. This pin can serve a variety of functions, including ones of
> questionable use to us on a GPIO header such as the 25MHz clock of the
> ethernet controller.
>
> Unfortunately, this is the precise function that it is being claimed for
> by the gmac0 node in the Sige5 board dts, meaning it can't be used for
> anything else despite serving no useful function in this role. Since it
> goes through a RS0108 bidirectional voltage level translator with a
> maximum data rate of 24Mbit/s in push-pull mode and 2Mbit/s data rate in
> open-drain mode, it's doubtful as to whether the 25MHz clock signal
> would even survive to the actual user-accessible pin it terminates in.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0
commit: 73d246b4402c3356f6b3d13665de3a51eea7b555
Actually applied this some days ago, but b4 is of the opinion,
I didn't sent out an applied-message yet, so doing that now :-) .
Best regards,
--
Heiko Stuebner <heiko@xxxxxxxxx>
