On 18/03/2025 10:26, Sai Krishna Musham wrote:
> const struct xilinx_cpm_variant *variant = port->variant;
> + struct device *dev = port->dev;
> + struct gpio_desc *reset_gpio;
> +
> + /* Request the GPIO for PCIe reset signal */
> + reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
> + if (IS_ERR(reset_gpio)) {
> + dev_err(dev, "Failed to request reset GPIO\n");
Isn't this probe path? If not, then why? How are you going to handle
deferrer probe?
> + return;> + }
> +
> + /* Assert the reset signal */
> + gpiod_set_value(reset_gpio, 1);
It was already asserted.
>
> - if (variant->version == CPM5NC_HOST)
> + /* Assert the PCIe IP reset */
> + writel_relaxed(0x1, port->crx_base + variant->cpm_pcie_rst);
> +
> + /* Controller specific delay */
> + udelay(50);
> +
> + /* Deassert the PCIe IP reset */
> + writel_relaxed(0x0, port->crx_base + variant->cpm_pcie_rst);
> +
> + /* Deassert the reset signal */
> + gpiod_set_value(reset_gpio, 0);
> + mdelay(PCIE_T_RRS_READY_MS);
> +
> + if (variant->version == CPM5NC_HOST) {
> + /* Clear Firewall */
> + writel_relaxed(0x00, port->cpm5nc_base +
> + XILINX_CPM5NC_PCIE0_FW);
> + writel_relaxed(0x01, port->cpm5nc_base +
> + XILINX_CPM5NC_PCIE0_FW);
> + writel_relaxed(0x00, port->cpm5nc_base +
> + XILINX_CPM5NC_PCIE0_FW);
> return;
> + }
>
> if (cpm_pcie_link_up(port))
> dev_info(port->dev, "PCIe Link is UP\n");
> @@ -551,6 +598,19 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
> port->reg_base = port->cfg->win;
> }
>
> + port->crx_base = devm_platform_ioremap_resource_byname(pdev,
> + "cpm_crx");
And here is the actual ABI break.
> + if (IS_ERR(port->crx_base))
> + return PTR_ERR(port->crx_base);
Best regards,
Krzysztof
