On Mon, Mar 17, 2025 at 10:01:10PM -0300, Maíra Canal wrote: > In order to enforce per-SoC register rules, add per-compatible > restrictions. For example, V3D 3.3 (used in brcm,7268-v3d) has a cache > controller (GCA), which is not present in other V3D generations. Declaring > these differences helps ensure the DTB accurately reflect the hardware > design. > > The example was using an incorrect order for the register names. This > commit corrects that by enforcing the order established in the register > items description. > > Signed-off-by: Maíra Canal <mcanal@xxxxxxxxxx> > --- > .../devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 86 ++++++++++++++++++---- > 1 file changed, 73 insertions(+), 13 deletions(-) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
