> Subject: Re: [PATCh v3 2/3] arm64: dts: freescale: Add basic dtsi for imx943
>
> On Thu, Mar 13, 2025 at 03:16:27PM +0800, Jacky Bai wrote:
> > Add the minimal dtsi support for i.MX943. i.MX943 is the first SoC of
> > i.MX94 Family, create a common dtsi for the whole i.MX94 family, and
> > the specific dtsi part for i.MX943.
> >
> > The clock, power domain and perf index need to be used by the device
> > nodes for resource reference, add them along with the dtsi support.
> >
> > Signed-off-by: Jacky Bai <ping.bai@xxxxxxx>
> > ---
> > - v3 changes:
> > - remove the blank line
> > - add PAD config macro define as suggested by Frank Li
> > - update the device nodes compatible strings for imx94 as suggested
> > by Krzysztof
> >
> > - v2 changes:
> > - remove the unnecessary macro define in clock header as suggested by
> Krzysztof
> > - split the dtsi into imx94.dtsi and imx943.dtsi
> > - use low case in the pinfunc header as Frank suggested
> > - reorder the device nodes and properties
> > ---
> ...
> > + aips2: bus@42000000 {
> > + compatible = "fsl,aips-bus", "simple-bus";
> > + reg = <0x0 0x42000000 0x0 0x800000>;
> > + ranges = <0x42000000 0x0 0x42000000 0x8000000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + edma2: dma-controller@42000000 {
> > + compatible = "fsl,imx94-edma5", "fsl,imx95-edma5";
> > + reg = <0x42000000 0x210000>;
> > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>;
> > + clock-names = "dma";
> > + #dma-cells = <3>;
> > + dma-channels = <64>;
> > + interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer
> 1>, <&a55_irqsteer 2>,
> > + <&a55_irqsteer 3>, <&a55_irqsteer 4>,
> <&a55_irqsteer 5>,
>
> Does below method work?
>
> interrupt-parent = <&a55_irqsteer>
> interrupts = <3>, <4>, <5>, ....
>
edma driver can not parse the irq correctly. The err irq is connected to GIC, not irqsteer.
> > + <&a55_irqsteer 6>, <&a55_irqsteer 7>,
> <&a55_irqsteer 8>,
> > + <&a55_irqsteer 9>, <&a55_irqsteer 10>,
> <&a55_irqsteer 11>,
> > + <&a55_irqsteer 12>, <&a55_irqsteer 13>,
> <&a55_irqsteer 14>,
> > + <&a55_irqsteer 15>, <&a55_irqsteer 16>,
> <&a55_irqsteer 17>,
> > + <&a55_irqsteer 18>, <&a55_irqsteer 19>,
> <&a55_irqsteer 20>,
> > + <&a55_irqsteer 21>, <&a55_irqsteer 22>,
> <&a55_irqsteer 23>,
> > + <&a55_irqsteer 24>, <&a55_irqsteer 25>,
> <&a55_irqsteer 26>,
> > + <&a55_irqsteer 27>, <&a55_irqsteer 28>,
> <&a55_irqsteer 29>,
> > + <&a55_irqsteer 30>, <&a55_irqsteer 31>,
> <&a55_irqsteer 64>,
> > + <&a55_irqsteer 65>, <&a55_irqsteer 66>,
> <&a55_irqsteer 67>,
> > + <&a55_irqsteer 68>, <&a55_irqsteer 69>,
> <&a55_irqsteer 70>,
> > + <&a55_irqsteer 71>, <&a55_irqsteer 72>,
> <&a55_irqsteer 73>,
> > + <&a55_irqsteer 74>, <&a55_irqsteer 75>,
> <&a55_irqsteer 76>,
> > + <&a55_irqsteer 77>, <&a55_irqsteer 78>,
> <&a55_irqsteer 79>,
> > + <&a55_irqsteer 80>, <&a55_irqsteer 81>,
> <&a55_irqsteer 82>,
> > + <&a55_irqsteer 83>, <&a55_irqsteer 84>,
> <&a55_irqsteer 85>,
> > + <&a55_irqsteer 86>, <&a55_irqsteer 87>,
> <&a55_irqsteer 88>,
>
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x0>;
>
> I remember compatible is first property, then reg.
>
Will change it as you suggested if no other comments for the order of device type and compatible.
BR
> Frank
> > + enable-method = "psci";
> > + #cooling-cells = <2>;
> > + cpu-idle-states = <&cpu_pd_wait>;
> > + power-domains = <&scmi_perf IMX94_PERF_A55>;
> > + power-domain-names = "perf";
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_cache_l0>;
> > + };
> > +
> > + cpu1: cpu@100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x100>;
> > + enable-method = "psci";
> > + #cooling-cells = <2>;
> > + cpu-idle-states = <&cpu_pd_wait>;
> > + power-domains = <&scmi_perf IMX94_PERF_A55>;
> > + power-domain-names = "perf";
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_cache_l1>;
> > + };
> > +
> > + cpu2: cpu@200 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x200>;
> > + enable-method = "psci";
> > + #cooling-cells = <2>;
> > + cpu-idle-states = <&cpu_pd_wait>;
> > + power-domains = <&scmi_perf IMX94_PERF_A55>;
> > + power-domain-names = "perf";
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_cache_l2>;
> > + };
> > +
> > + cpu3: cpu@300 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x300>;
> > + enable-method = "psci";
> > + #cooling-cells = <2>;
> > + cpu-idle-states = <&cpu_pd_wait>;
> > + power-domains = <&scmi_perf IMX94_PERF_A55>;
> > + power-domain-names = "perf";
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_cache_l3>;
> > + };
> > +
> > + l2_cache_l0: l2-cache-l0 {
> > + compatible = "cache";
> > + cache-size = <65536>;
> > + cache-line-size = <64>;
> > + cache-sets = <256>;
> > + cache-level = <2>;
> > + cache-unified;
> > + next-level-cache = <&l3_cache>;
> > + };
> > +
> > + l2_cache_l1: l2-cache-l1 {
> > + compatible = "cache";
> > + cache-size = <65536>;
> > + cache-line-size = <64>;
> > + cache-sets = <256>;
> > + cache-level = <2>;
> > + cache-unified;
> > + next-level-cache = <&l3_cache>;
> > + };
> > +
> > + l2_cache_l2: l2-cache-l2 {
> > + compatible = "cache";
> > + cache-size = <65536>;
> > + cache-line-size = <64>;
> > + cache-sets = <256>;
> > + cache-level = <2>;
> > + cache-unified;
> > + next-level-cache = <&l3_cache>;
> > + };
> > +
> > + l2_cache_l3: l2-cache-l3 {
> > + compatible = "cache";
> > + cache-size = <65536>;
> > + cache-line-size = <64>;
> > + cache-sets = <256>;
> > + cache-level = <2>;
> > + cache-unified;
> > + next-level-cache = <&l3_cache>;
> > + };
> > +
> > + l3_cache: l3-cache {
> > + compatible = "cache";
> > + cache-size = <1048576>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <3>;
> > + cache-unified;
> > + };
> > + };
> > +};
> > --
> > 2.34.1
> >
