On Sat, Mar 15, 2025 at 03:15:45PM -0500, Bjorn Helgaas wrote:
> From: Frank Li <Frank.Li@xxxxxxx>
>
> Endpoint
> ┌───────────────────────────────────────────────┐
> │ pcie-ep@5f010000 │
> │ ┌────────────────┐│
> │ │ Endpoint ││
> │ │ PCIe ││
> │ │ Controller ││
> │ bus@5f000000 │ ┌────────►
> │ ┌──────────┐ │ │ ││dynamically
> │ │ │ Outbound Transfer │ ││allocated
> │┌─────┐ │ Bus ┼─────►│ ATU ───────┘ ││PCI Addr
> ││ │ │ Fabric │Bus │ ││
> ││ CPU ├───►│ │Addr │ ││
> ││ │CPU │ │0x8000_0000 ││
> │└─────┘Addr└──────────┘ │ ││
> │ 0x7000_0000 └────────────────┘│
> └───────────────────────────────────────────────┘
>
> bus@5f000000 {
> compatible = "simple-bus";
> ranges = <0x80000000 0x0 0x70000000 0x10000000>;
>
> pcie-ep@5f010000 {
> reg = <0x80000000 0x10000000>;
> reg-names ="addr_space";
> ...
> };
> ...
> };
>
> In the diagram above, CPU writes data to outbound window address
> 0x7000_0000, and the bus fabric maps it to 0x8000_0000. The ATU uses
> bus address 0x8000_0000 as input address and maps to some PCI address
> dynamically allocated by a PCI device driver on the host side.
>
> The pcie-ep@5f010000 'reg[addr_space]' is the parent bus address of the
> PCIe controller input, including the ATU.
how about
The pcie-ep@5f010000 'reg[addr_space]' is the parent bus address, which is
input of PCIe controller including the ATU.
Frank
>
> Set parent_bus_offset, the offset from the CPU address to the PCIe
> controller input address using dw_pcie_init_parent_bus_offset(). The
> parent_bus_offset is not used yet, so no functional change intended.
>
> Link: https://lore.kernel.org/r/20250313-pci_fixup_addr-v11-7-01d2313502ab@xxxxxxx
> Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> [bhelgaas: commit log]
> Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 2db834345ec2..bb87d0c5c665 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -904,6 +904,13 @@ static int dw_pcie_ep_get_resources(struct dw_pcie_ep *ep)
> ep->phys_base = res->start;
> ep->addr_size = resource_size(res);
>
> + /*
> + * artpec6_pcie_cpu_addr_fixup() uses ep->phys_base, so call
> + * dw_pcie_parent_bus_offset() after setting ep->phys_base.
> + */
> + pci->parent_bus_offset = dw_pcie_parent_bus_offset(pci, "addr_space",
> + ep->phys_base);
> +
> ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
> if (ret < 0)
> epc->max_functions = 1;
> --
> 2.34.1
>
