The current EPP, ISP and MPE schemas are largely compatible with Tegra114 and Tegra124, requiring only minor adjustments. Additionally, the TSEC schema for the Security engine, which is available from Tegra114 onwards, is included. Signed-off-by: Svyatoslav Ryhel <clamor95@xxxxxxxxx> --- .../display/tegra/nvidia,tegra114-tsec.yaml | 66 +++++++++++++++++++ .../display/tegra/nvidia,tegra20-epp.yaml | 14 ++-- .../display/tegra/nvidia,tegra20-isp.yaml | 14 ++-- .../display/tegra/nvidia,tegra20-mpe.yaml | 18 +++-- 4 files changed, 99 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml new file mode 100644 index 000000000000..c66ac6a6538e --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Security co-processor + +maintainers: + - Svyatoslav Ryhel <clamor95@xxxxxxxxx> + - Thierry Reding <thierry.reding@xxxxxxxxx> + +description: Tegra Security co-processor, an embedded security processor used + mainly to manage the HDCP encryption and keys on the HDMI link. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra114-tsec + - nvidia,tegra124-tsec + + - items: + - const: nvidia,tegra132-tsec + - const: nvidia,tegra124-tsec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: tsec + + iommus: + maxItems: 1 + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the core power domain + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra114-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tsec@54500000 { + compatible = "nvidia,tegra114-tsec"; + reg = <0x54500000 0x00040000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_TSEC>; + resets = <&tegra_car TEGRA114_CLK_TSEC>; + reset-names = "tsec"; + }; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml index 3c095a5491fe..334f5531b243 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml @@ -15,10 +15,16 @@ properties: pattern: "^epp@[0-9a-f]+$" compatible: - enum: - - nvidia,tegra20-epp - - nvidia,tegra30-epp - - nvidia,tegra114-epp + oneOf: + - enum: + - nvidia,tegra20-epp + - nvidia,tegra30-epp + - nvidia,tegra114-epp + - nvidia,tegra124-epp + + - items: + - const: nvidia,tegra132-epp + - const: nvidia,tegra124-epp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml index 3bc3b22e98e1..fbfcabb58fd5 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml @@ -12,10 +12,16 @@ maintainers: properties: compatible: - enum: - - nvidia,tegra20-isp - - nvidia,tegra30-isp - - nvidia,tegra210-isp + oneOf: + - enum: + - nvidia,tegra20-isp + - nvidia,tegra30-isp + - nvidia,tegra114-isp + - nvidia,tegra124-isp + + - items: + - const: nvidia,tegra132-isp + - const: nvidia,tegra124-isp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml index 2cd3e60cd0a8..36b76fa8f525 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml @@ -12,13 +12,21 @@ maintainers: properties: $nodename: - pattern: "^mpe@[0-9a-f]+$" + oneOf: + - pattern: "^mpe@[0-9a-f]+$" + - pattern: "^msenc@[0-9a-f]+$" compatible: - enum: - - nvidia,tegra20-mpe - - nvidia,tegra30-mpe - - nvidia,tegra114-mpe + oneOf: + - enum: + - nvidia,tegra20-mpe + - nvidia,tegra30-mpe + - nvidia,tegra114-msenc + - nvidia,tegra124-msenc + + - items: + - const: nvidia,tegra132-msenc + - const: nvidia,tegra124-msenc reg: maxItems: 1 -- 2.43.0
