On Thursday 07 May 2015 19:01:13 Brian Norris wrote:
>
> Would this satisfy you?
>
> From: Brian Norris <computersforpeace@xxxxxxxxx>
> Date: Tue, 5 May 2015 17:46:42 -0700
> Subject: [PATCH] mtd: brcmstb_nand: fixup endianness assumptions
>
> All users of this controller (MIPS or ARM) have previously used native
> I/O (__raw{read,write}l()) to access registers. This is normal for the
> MIPS case, where BMIPS chips often have a boot-strap that configures not
> only the CPU, but also all the busing, to use a given endianness.
> However, newer ARM cores support switching to big endian mode at
> runtime, which would leave us with different bus and CPU endianness. For
> these cases, we should use the endian-switching accessors, so we
> continue to access the NAND core in little endian mode.
>
> Suggested by Arnd.
>
> Signed-off-by: Brian Norris <computersforpeace@xxxxxxxxx>
> ---
>
Yes, looks good, thanks!
Arnd
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