On 03/03/2025 23:53, Dmitry Baryshkov wrote:
On Tue, Mar 04, 2025 at 12:55:21AM +0200, Vladimir Zapolskiy wrote:
SM8550 Camera Clock Controller shall enable both MXC and MMCX power
domains.
Are those really required to access the registers of the cammcc? Or is
one of those (MXC?) required to setup PLLs? Also, is this applicable
only to sm8550 or to other similar clock controllers?
Fixes: e271b59e39a6f ("arm64: dts: qcom: sm8550: Add camera clock controller")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index d02d80d731b9..d22b1753d521 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3329,7 +3329,8 @@ camcc: clock-controller@ade0000 {
<&bi_tcxo_div2>,
<&bi_tcxo_ao_div2>,
<&sleep_clk>;
- power-domains = <&rpmhpd SM8550_MMCX>;
+ power-domains = <&rpmhpd SM8550_MXC>,
+ <&rpmhpd SM8550_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.43.0
I think both of these are required.
Its a pattern we see again and again with videocc and camcc controllers.
The GDSCs and => the hard-coded always on PLLs need to ensure these
rails are on.
---
bod
