On Tue, Mar 11, 2025 at 01:04:23PM +0530, Pinkesh Vaghela wrote: > From: Darshan Prajapati <darshan.prajapati@xxxxxxxxxxxxxx> > > Update Documentation for supporting SiFive P550 based CPU > > Signed-off-by: Darshan Prajapati <darshan.prajapati@xxxxxxxxxxxxxx> > Reviewed-by: Samuel Holland <samuel.holland@xxxxxxxxxx> > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@xxxxxxxxxxxxxx> Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 2c72f148a74b..3ee7468001f6 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -51,6 +51,7 @@ properties: > - sifive,e5 > - sifive,e7 > - sifive,e71 > + - sifive,p550 > - sifive,rocket0 > - sifive,s7 > - sifive,u5 > -- > 2.25.1 >
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