On Mon, Mar 10, 2025 at 12:07:17PM -0500, Bjorn Helgaas wrote:
> On Mon, Feb 24, 2025 at 09:20:24PM +0530, Thippeswamy Havalige wrote:
> > The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> > incorporate the Coherency and PCIe Gen5 Module, specifically the
> > Next-Generation Compact Module (CPM5NC).
> >
> > The integrated CPM5NC block, along with the built-in bridge, can function
> > as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
> > rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
> > configuration.
> >
> > Bridge errors are managed using a specific interrupt line designed for
> > CPM5N. INTx interrupt support is not available.
> >
> > Currently in this commit platform specific Bridge errors support is not
> > added.
>
> > @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
> > {
> > const struct xilinx_cpm_variant *variant = port->variant;
> >
> > + if (variant->version != CPM5NC_HOST)
> > + return;
>
> You're adding support for CPM5NC_HOST, but this changes the behavior
> for all the NON-CPM5NC_HOST devices, which looks like a typo.
>
> Should it be "variant->version == CPM5NC_HOST" instead?
Thanks for your patch that fixes this part.
> Also, this makes it look like CPM5NC_HOST doesn't support any
> interrupts at all. No INTx, no MSI, no MSI-X. Is that true? If so,
> what good is a host controller where interrupts don't work?
Does this controller support interrupts?
