On Mon, Mar 10, 2025 at 12:08:32PM +0800, Inochi Amaoto wrote: > On Thu, 27 Feb 2025 07:23:17 +0800, Inochi Amaoto wrote: > > The clock controller of SG2044 provides multiple clocks for various > > IPs on the SoC, including PLL, mux, div and gates. As the PLL and > > div have obvious changed and do not fit the framework of SG2042, > > a new implement is provided to handle these. > > > > Changed from v2: > > 1. Applied Chen Wang' tag > > 2. patch 2: fix author mail infomation > > > > [...] > > Applied to for-next, thanks! > > [1/2] dt-bindings: clock: sophgo: add clock controller for SG2044 > https://github.com/sophgo/linux/commit/0332ae22ce09ce64f5e54fc2a24ed22073dbeb9d > [2/2] clk: sophgo: Add clock controller support for SG2044 SoC > https://github.com/sophgo/linux/commit/fcee6f2173e7f7fb39f35899faea282fd9b5ea30 > > Thanks, > Inochi > Please ignore this mail, this point to a wrong url. Regards, Inochi
