Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.
Add device tree nodes for the two Ethernet controllers in RK3528.
Signed-off-by: Jonas Karlman <jonas@xxxxxxxxx>
---
Changes in v2:
- Add ethernet-phy@2 for the integrated PHY
I have no board that expose an Ethernet port for the gmac0 and the
integrated PHY. However, the PHY can be identified on addr 0x2 as
0044.1400 and in vendor kernel this relate to the Rockchip RK630 PHY.
A proper PHY driver will be needed to support real use of gmac0.
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 105 +++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 4c0a25cc089c..56ced7c640f1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -678,6 +678,111 @@ saradc: adc@ffae0000 {
status = "disabled";
};
+ gmac0: ethernet@ffbd0000 {
+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xffbd0000 0x0 0x10000>;
+ clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
+ <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
+ <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "mac_clk_rx", "mac_clk_tx",
+ "pclk_mac", "aclk_mac";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ phy-handle = <&rmii0_phy>;
+ phy-mode = "rmii";
+ resets = <&cru SRST_A_MAC_VO>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&vo_grf>;
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ rmii0_phy: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x2>;
+ clocks = <&cru CLK_MACPHY>;
+ phy-is-integrated;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fephym0_led_link>,
+ <&fephym0_led_spd>;
+ resets = <&cru SRST_MACPHY>;
+ };
+ };
+
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ gmac1: ethernet@ffbe0000 {
+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xffbe0000 0x0 0x10000>;
+ clocks = <&cru CLK_GMAC1_SRC_VPU>,
+ <&cru CLK_GMAC1_RMII_VPU>,
+ <&cru PCLK_MAC_VPU>,
+ <&cru ACLK_MAC_VPU>;
+ clock-names = "stmmaceth",
+ "clk_mac_ref",
+ "pclk_mac",
+ "aclk_mac";
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ resets = <&cru SRST_A_MAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&vpu_grf>;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
sdhci: mmc@ffbf0000 {
compatible = "rockchip,rk3528-dwcmshc",
"rockchip,rk3588-dwcmshc";
--
2.48.1
