On Sun, Mar 09, 2025 at 06:26:52PM +0100, Christian Marangi wrote: > +/* If a non empty valid_addr_mask is passed, PHY address and > + * read/write register are encoded in the regmap register > + * by placing the register in the first 16 bits and the PHY address > + * right after. > + */ > +#define MDIO_REGMAP_PHY_ADDR GENMASK(20, 16) > +#define MDIO_REGMAP_PHY_REG GENMASK(15, 0) Clause 45 PHYs have 5 bits of PHY address, then 5 bits of mmd address, and then 16 bits of register address - significant in that order. Can we adjust the mask for the PHY address later to add the MMD between the PHY address and register number? -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
