On Wed, May 06, 2015 at 09:12:43PM +0200, Arnd Bergmann wrote:
> On Wednesday 06 May 2015 10:59:50 Brian Norris wrote:
> > + /*
> > + * Some SoCs integrate this controller (e.g., its interrupt bits) in
> > + * interesting ways
> > + */
> > + if (of_property_read_bool(dn, "brcm,nand-soc")) {
> > + struct device_node *soc_dn;
> > +
> > + soc_dn = of_parse_phandle(dn, "brcm,nand-soc", 0);
> > + if (!soc_dn)
> > + return -ENODEV;
> > +
> > + ctrl->soc = devm_brcmnand_probe_soc(dev, soc_dn);
> > + if (!ctrl->soc) {
> > + dev_err(dev, "could not probe SoC data\n");
> > + of_node_put(soc_dn);
> > + return -ENODEV;
> > + }
> > +
> > + ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
> > + DRV_NAME, ctrl);
> > +
> > + /* Enable interrupt */
> > + ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
> > +
> > + of_node_put(soc_dn);
> > + } else {
> > + /* Use standard interrupt infrastructure */
> > + ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
> > + DRV_NAME, ctrl);
> > + }
> >
>
> It looks to me like this should be handled as a nested irqchip, so the node
> you look up gets used as the "interrupt-parent" instead, making the behavior
> of this SoC transparent to the nand driver.
You snipped the rest of the patch, which involves more than just IRQ
handling. The same registers touch both interrupts and data bus endian
configuration, so it can't possibly be done transparently to the NAND
driver.
> We recently merged nested irqdomain support as well, which might help here,
> or might not be needed.
I'm not familiar with nested irqdomains. Do they address anything like
the above problem?
Brian
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