On Wednesday 06 May 2015 10:59:47 Brian Norris wrote:
> +
> +static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
> +{
> + return __raw_readl(ctrl->nand_base + offs);
> +}
> +
> +static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
> + u32 val)
> +{
> + __raw_writel(val, ctrl->nand_base + offs);
> +}
> +
>
You had mentioned previously that there might be an endianess issue in this
driver. I think this won't work on big-endian architectures other than MIPS,
so it would be good to either list in the DT the endianess of the device
and use appropriate accessors here, or hardcode it based on the architecture
(using ioread32_be in big-endian mips, but readl elsewhere).
Using __raw_writel has another problem regarding the DMA capability of this
driver, as it will not flush any write buffers or synchronize caches before
sending data off to the device, so you risk data corruption. Also, the
compiler can choose to split up the 32-bit word access into byte accesses,
which on most hardware does not do what you want.
Arnd
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