The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux
selection bits, reset assertion bit and enable bits for function and bus
clocks. It has a quirk that reading always results in zero.
As a workaround, let's hardcode the mux value as zero to select
pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask
is combined from the real bus and function clocks to avoid the
write-only register being shared between two clk_hws, in which case
updates of one clk_hw zero the other's bits.
With a 1:1 factor serving as placeholder for the bus clock, the I2C-8
controller could be brought up, which is essential for boards attaching
power-management chips to it.
Signed-off-by: Haylen Chu <heylenay@xxxxxxx>
---
drivers/clk/spacemit/ccu-k1.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
index 5974a0a1b5f6..44db48ae7131 100644
--- a/drivers/clk/spacemit/ccu-k1.c
+++ b/drivers/clk/spacemit/ccu-k1.c
@@ -558,6 +558,10 @@ static CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents,
APBC_TWSI7_CLK_RST,
4, 3, BIT(1),
0);
+static CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5),
+ APBC_TWSI8_CLK_RST,
+ BIT(1) | BIT(0),
+ 0);
static const struct clk_parent_data timer_parents[] = {
CCU_PARENT_HW(pll1_d192_12p8),
@@ -795,6 +799,8 @@ static CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk),
APBC_TWSI7_CLK_RST,
BIT(0),
0);
+static CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk),
+ 1, 1);
static CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk),
APBC_TIMERS1_CLK_RST,
--
2.48.1
