> The container node has a #address-cells property for this very reason. It's > perfectly well-defined how to split up a property containing a large number > of cells into separate values, by using the value of #address-cells. Plus, > the canonical formatting (albeit not enforced by the DT compiler) for a > property that contains an array of entries, each 2 cells in size, would be: > > reg = <0 0x1a>, <0 0x40>, <0 0x48>; > > rather than: > > reg = <0 0x1a 0 0x40 0 0x48>; > > ... so it's quite simple to make it very human-readable too. I give in to the flag idea. I also noticed that we'd need another flag anyhow to mark 10 bit addresses. I am still thinking between using two address-cells in that case (clean seperation between address and flags) or to encode the flags as MSB in the current address (all busses will have same address-cells and child description, less code paths and no overhead in dtbs). That being said, for the loopback testcase, the I2C slave framework will need updates as well. I think I can cook up something. Will be interesting to see if my hardware can do this. Has the loopback already been tested on Tegra?
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