Move PCIe nodes under bus@c0000000 to correctly reflect hardware behavior.
Use ranges in bus@c0000000 to indicate address translation, as the bus
fabric trims CPU address 0xc000_0000..0xdfff_ffff to
0x0000_0000..0x1fff_ffff.
Set 'config' and 'addr_space' reg values to 0.
Change parent bus address of downstream I/O and non-prefetchable memory to
0.
Ensure no functional impact on the final address translation result.
Prepare for the removal of the driver’s cpu_addr_fixup().
Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
---
arch/arm/boot/dts/axis/artpec6.dtsi | 92 ++++++++++++++++++++-----------------
1 file changed, 50 insertions(+), 42 deletions(-)
diff --git a/arch/arm/boot/dts/axis/artpec6.dtsi b/arch/arm/boot/dts/axis/artpec6.dtsi
index 037157e6c5ee3..399e87f72865f 100644
--- a/arch/arm/boot/dts/axis/artpec6.dtsi
+++ b/arch/arm/boot/dts/axis/artpec6.dtsi
@@ -155,49 +155,57 @@ pmu {
interrupt-affinity = <&cpu0>, <&cpu1>;
};
- /*
- * Both pci nodes cannot be enabled at the same time,
- * leave the unwanted node as disabled.
- */
- pcie: pcie@f8050000 {
- compatible = "axis,artpec6-pcie", "snps,dw-pcie";
- reg = <0xf8050000 0x2000
- 0xf8040000 0x1000
- 0xc0000000 0x2000>;
- reg-names = "dbi", "phy", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- /* downstream I/O */
- ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
- /* non-prefetchable memory */
- 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
- num-lanes = <2>;
- bus-range = <0x00 0xff>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- axis,syscon-pcie = <&syscon>;
- status = "disabled";
- };
+ bus@c0000000 {
+ compatible = "simple-bus";
+ ranges = <0x0 0xc0000000 0x20000000>,
+ <0xf8000000 0xf8000000 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- pcie_ep: pcie_ep@f8050000 {
- compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
- reg = <0xf8050000 0x2000
- 0xf8051000 0x2000
- 0xf8040000 0x1000
- 0xc0000000 0x20000000>;
- reg-names = "dbi", "dbi2", "phy", "addr_space";
- num-ib-windows = <6>;
- num-ob-windows = <2>;
- num-lanes = <2>;
- axis,syscon-pcie = <&syscon>;
- status = "disabled";
+ /*
+ * Both pci nodes cannot be enabled at the same time,
+ * leave the unwanted node as disabled.
+ */
+ pcie: pcie@f8050000 {
+ compatible = "axis,artpec6-pcie", "snps,dw-pcie";
+ reg = <0xf8050000 0x2000
+ 0xf8040000 0x1000
+ 0x00000000 0x2000>;
+ reg-names = "dbi", "phy", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ /* downstream I/O */
+ ranges = <0x81000000 0 0 0x00002000 0 0x00010000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xc0012000 0x00012000 0 0x1ffee000>;
+ num-lanes = <2>;
+ bus-range = <0x00 0xff>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ axis,syscon-pcie = <&syscon>;
+ status = "disabled";
+ };
+
+ pcie_ep: pcie_ep@f8050000 {
+ compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
+ reg = <0xf8050000 0x2000
+ 0xf8051000 0x2000
+ 0xf8040000 0x1000
+ 0x00000000 0x20000000>;
+ reg-names = "dbi", "dbi2", "phy", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ num-lanes = <2>;
+ axis,syscon-pcie = <&syscon>;
+ status = "disabled";
+ };
};
pinctrl: pinctrl@f801d000 {
--
2.34.1
