On Tue, Mar 04, 2025 at 03:12:37PM +0800, Inochi Amaoto wrote: > The pcie controller on the SG2044 is designware based with > custom app registers. > > Add binding document for SG2044 PCIe host controller. > > Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxx> > --- > .../bindings/pci/sophgo,sg2044-pcie.yaml | 122 ++++++++++++++++++ > 1 file changed, 122 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml > new file mode 100644 > index 000000000000..2860d0f13146 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml > @@ -0,0 +1,122 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/sophgo,sg2044-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: DesignWare based PCIe Root Complex controller on Sophgo SoCs > + > +maintainers: > + - Inochi Amaoto <inochiama@xxxxxxxxx> > + > +description: |+ Don't need '|+' if no formatting to preserve. With that, Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
