On 3/3/25 18:46, Krzysztof Kozlowski wrote: > On 03/03/2025 18:41, Krzysztof Kozlowski wrote: >> On 03/03/2025 15:36, Michal Wilczynski wrote: >>> Add device tree bindings for the TH1520 Video Output (VO) subsystem >>> clock controller. The VO sub-system manages clock gates for multimedia >>> components including HDMI, MIPI, and GPU. >>> >>> Document the VIDEO_PLL requirements for the VO clock controller, which >>> receives its input from the AP clock controller. The VIDEO_PLL is a >>> Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz >>> with maximum FOUTVCO of 2376 MHz. >>> >>> Add a mandatory reset property for the TH1520 VO clock controller that >>> handles the GPU clocks. This reset line controls the GPU CLKGEN reset, >>> which is required for proper GPU clock operation. >>> >>> The reset property is only required for the "thead,th1520-clk-vo" >>> compatible, as it specifically handles the GPU-related clocks. >>> >>> This binding complements the existing AP sub-system clock controller >>> which manages CPU, DPU, GMAC and TEE PLLs. >>> >>> Signed-off-by: Michal Wilczynski <m.wilczynski@xxxxxxxxxxx> >>> --- >>> .../bindings/clock/thead,th1520-clk-ap.yaml | 33 ++++++++++++++++-- >>> .../dt-bindings/clock/thead,th1520-clk-ap.h | 34 +++++++++++++++++++ >>> 2 files changed, 64 insertions(+), 3 deletions(-) >> >> >> Where is the changelog? Why is this v1? There was extensive discussion >> for many versions, so does it mean all of it was ignored? > > > Plus this was reviewed so it is even more confusing. Where is the review > tag? If tag was dropped, you must explain this - see submitting patches, > which asks for that. There was a tag, but later in v5 I've added another part to this dt-binding - reset, which I wasn't sure whether you would approve of, so I've removed the Reviewed-by. > > Best regards, > Krzysztof >
