On Mon, Mar 03, 2025 at 11:24:35PM +0800, Ziyang Huang wrote:
> Current example use external PHY. With the previous patch, internal PHY
> is also supported.
>
> Signed-off-by: Ziyang Huang <hzyitc@xxxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/net/dsa/qca8k.yaml | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.yaml b/Documentation/devicetree/bindings/net/dsa/qca8k.yaml
> index 167398ab253a..a71dc38d6bab 100644
> --- a/Documentation/devicetree/bindings/net/dsa/qca8k.yaml
> +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.yaml
> @@ -185,8 +185,10 @@ examples:
> };
>
> port@4 {
> + /* PHY-to-PHY CPU link */
> reg = <4>;
> - label = "lan4";
> + ethernet = <&gmac2>;
> + phy-mode = "gmii";
> phy-handle = <&external_phy_port4>;
> };
>
> @@ -266,8 +268,9 @@ examples:
> };
>
> port@4 {
> + /* PHY-to-PHY CPU link */
> reg = <4>;
> - label = "lan4";
> + ethernet = <&gmac2>;
> phy-mode = "internal";
> phy-handle = <&internal_phy_port4>;
> };
Adding some more context:
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&internal_phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&internal_phy_port5>;
};
port@6 {
reg = <0>;
ethernet = <&gmac1>;
phy-mode = "sgmii";
qca,sgmii-rxclk-falling-edge;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
The previous patch still causes it to look at port 0 and then port 6
first. Only if they are not CPU ports will it look at other ports. So
this example does not work, port 6 will be the CPU port, even with the
properties you added.
When you fix this, i also think it would be good to extend:
> + /* PHY-to-PHY CPU link */
with the work internal.
This also seems an odd architecture to me. If this is SoC internal,
why not do a MAC to MAC link? What benefit do you get from having the
PHYs?
Andrew
---
pw-bot: cr
