On 2/27/25 17:52, Ryan.Wanner@xxxxxxxxxxxxx wrote:
From: Ryan Wanner <Ryan.Wanner@xxxxxxxxxxxxx>
Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able
to store the RTT time data.
Signed-off-by: Ryan Wanner <Ryan.Wanner@xxxxxxxxxxxxx>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index b0a676623100..aadeea132289 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -120,6 +120,13 @@ shdwc: poweroff@e001d200 {
status = "disabled";
};
+ rtt: rtc@e001d300 {
+ compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
+ reg = <0xe001d300 0x30>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk32k 0>;
+ };
+
clk32k: clock-controller@e001d500 {
compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
reg = <0xe001d500 0x4>;
@@ -132,6 +139,11 @@ chipid@e0020000 {
reg = <0xe0020000 0x8>;
};
+ gpbr: gpbr@e001d700 {
+ compatible = "microchip,sama7d65-gpbr", "syscon";
+ reg = <0xe001d700 0x48>;
+ };
This node should be before chipid one to have them sorted by node address.
+
dma2: dma-controller@e1200000 {
compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
reg = <0xe1200000 0x1000>;
