On Fri, Feb 28, 2025 at 08:40:23PM +0800, Zixian Zeng wrote: > Add spi controllers for SG2042. > > SG2042 uses the upstreamed Synopsys DW SPI IP. > > Signed-off-by: Zixian Zeng <sycamoremoon376@xxxxxxxxx> > --- > For this spi controller patch, only bindings are included. > This is tested on milkv-pioneer board. Using driver/spi/spidev.c > for creating /dev/spidevX.Y and tools/spi/spidev_test for testing > functionality. I wonder whether this patch is tested (or at least can be tested), as I am not sure there are pins for spi or any onboard device on existing SG2042 board. > --- > Changes in v2: > - rebase v1 to sophgo/master(github.com/sophgo/linux.git). > - order properties in device node. > - remove unevaluated properties `clock-frequency`. > - set default status to disable. > - Link to v1: https://lore.kernel.org/r/20250228-sfg-spi-v1-1-b989aed94911@xxxxxxxxx > --- > .../riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 8 +++++++ > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 28 ++++++++++++++++++++++ > 2 files changed, 36 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts > index be596d01ff8d33bcdbe431d9731a55ee190ad5b3..c43a807af2f827b5267afe5e4fdf6e9e857dfa20 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts > +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts > @@ -72,6 +72,14 @@ &uart0 { > status = "okay"; > }; > > +&spi0 { > + status = "okay"; > +}; > + > +&spi1 { > + status = "okay"; > +}; > + > / { > thermal-zones { > soc-thermal { > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > index e62ac51ac55abd922b5ef796ba8c2196383850c4..500645147b1f8ed0a08ad3cafb38ea79cf57d737 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > @@ -545,5 +545,33 @@ sd: mmc@704002b000 { > "timer"; > status = "disabled"; > }; > + > + spi0: spi@7040004000 { > + compatible = "snps,dw-apb-ssi"; > + reg = <0x70 0x40004000 0x00 0x1000>; > + clocks = <&clkgen GATE_CLK_APB_SPI>, > + <&clkgen GATE_CLK_SYSDMA_AXI>; Is the sysdma axi clock for the this device. IIRC is APB interface. Also, Are these clock aligned? If not, use space to align the two clocks. You also need to add the clock-names here. > + interrupt-parent = <&intc>; > + interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <0x01>; > + #size-cells = <0x00>; > + num-cs = <0x02>; Just use decimal number, no hex there. > + resets = <&rstgen RST_SPI0>; > + status = "disabled"; > + }; > + > + spi1: spi@7040005000 { > + compatible = "snps,dw-apb-ssi"; > + reg = <0x70 0x40005000 0x00 0x1000>; > + clocks = <&clkgen GATE_CLK_APB_SPI>, > + <&clkgen GATE_CLK_SYSDMA_AXI>; The same as above. > + interrupt-parent = <&intc>; > + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <0x01>; > + #size-cells = <0x00>; > + num-cs = <0x02>; The same as above. > + resets = <&rstgen RST_SPI1>; > + status = "disabled"; > + }; > }; > }; > > --- > base-commit: aa5ee7180ec41bb77c3e327e95d119f2294babea > change-id: 20250228-sfg-spi-e3f2aeca09ab > > Best regards, > -- > Zixian Zeng <sycamoremoon376@xxxxxxxxx> >
