On 2/6/25 19:01, Hal Feng wrote:
>> On 06.02.25 19:17, E Shattow wrote:
>> On 2/5/25 18:59, Hal Feng wrote:
>>> On 2/5/2025 6:01 PM, Heinrich Schuchardt wrote:
>>>> On 2/5/25 08:57, Hal Feng wrote:
>>>>> On 2/3/2025 9:37 AM, E Shattow wrote:
>>>>>> Add bootph-pre-ram hinting to jh7110-common.dtsi:
>>>>>> - i2c5_pins and i2c-pins subnode for connection to eeprom
>>>>>> - eeprom node
>>>>>> - qspi flash configuration subnode
>>>>>> - memory node
>>>>>> - uart0 for serial console
>>>>>>
>>>>>> With this the U-Boot SPL secondary program loader may drop such
>>>>>> overrides when using dt-rebasing with JH7110 OF_UPSTREAM board
>> targets.
>>>>>>
>>>>>> Signed-off-by: E Shattow <e@xxxxxxxxxxxx>
>>>>>> ---
>>>>>> arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++
>>>>>> 1 file changed, 6 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
>>>>>> b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
>>>>>> index 30c5f3487c8b..c9e7ae59ee7c 100644
>>>>>> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
>>>>>> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
>>>>>> @@ -28,6 +28,7 @@ chosen {
>>>>>> memory@40000000 {
>>>>>> device_type = "memory";
>>>>>> reg = <0x0 0x40000000 0x1 0x0>;
>>>>>> + bootph-pre-ram;
>>>>>> };
>>>>>> gpio-restart {
>>>>>> @@ -247,6 +248,7 @@ emmc_vdd: aldo4 {
>>>>>> };
>>>>>> eeprom@50 {
>>>>>> + bootph-pre-ram;
>>>>>> compatible = "atmel,24c04";
>>>>>> reg = <0x50>;
>>>>>> pagesize = <16>;
>>>>>> @@ -323,6 +325,7 @@ &qspi {
>>>>>> nor_flash: flash@0 {
>>>>>> compatible = "jedec,spi-nor";
>>>>>> reg = <0>;
>>>>>> + bootph-pre-ram;
>>>>>> cdns,read-delay = <2>;
>>>>>> spi-max-frequency = <100000000>;
>>>>>> cdns,tshsl-ns = <1>;
>>>>>> @@ -405,6 +408,7 @@ GPOEN_SYS_I2C2_DATA,
>>>>>> };
>>>>>> i2c5_pins: i2c5-0 {
>>>>>> + bootph-pre-ram;
>>>>>> i2c-pins {
>>>>>> pinmux = <GPIOMUX(19, GPOUT_LOW,
>>>>>> GPOEN_SYS_I2C5_CLK, @@ -413,6 +417,7 @@
>>>>>> GPI_SYS_I2C5_CLK)>,
>>>>>> GPOEN_SYS_I2C5_DATA,
>>>>>> GPI_SYS_I2C5_DATA)>;
>>>>>> bias-disable; /* external pull-up */
>>>>>> + bootph-pre-ram;
>>>>>> input-enable;
>>>>>> input-schmitt-enable;
>>>>>> };
>>>>>> @@ -641,6 +646,7 @@ GPOEN_DISABLE,
>>>>>> };
>>>>>> &uart0 {
>>>>>> + bootph-pre-ram;
>>>>>> clock-frequency = <24000000>;
>>>>>> pinctrl-names = "default";
>>>>>> pinctrl-0 = <&uart0_pins>;
>>>>>
>>>>> What about &mmc0, &mmc1, &qspi, &sysgpio, &mmc0_pins,
>> &mmc1_pins, &i2c5?
>>>>> Why not add "bootph-pre-ram;" for them?
>>>>
>>>> Would they be needed before relocation of U-Boot to DRAM?
>>>
>>> Yeah, they are needed by SPL and they are set in U-Boot
>>> arch/riscv/dts/jh7110-common-u-boot.dtsi.
>>>
>>> Best regards,
>>> Hal
>>>
>>
>> When I tested on Star64 there was none of those needed to boot. We can add
>> more bootph-pre-ram as needed but I want to know how to test (because I
>> did not see any need for these).
>>
>> How do you test that these are needed?
>
> In my opinion, SPL need to read U-Boot from EMMC (mmc0) or SDcard (mmc1) or
> QSPI flash (qspi). Also it need to choose the correct DTB by reading EEPROM
> mounted on i2c5. To run mmc / i2c drivers, the pin configurations (sysgpio, mmc0/1_pins)
> are also needed.
>
> Best regards,
> Hal
EMMC or SDcard are not possible to boot (via JH7110 boot ROM, distinct
from QSPI boot of U-Boot and later EMMC or SDcard capability) in this
way on some of the boards where transistor logic pairs GPIO0 and GPIO1
both-off or both-on. SDcard boot is officially recommended against as
"not supported" by the StarFive reference documentation, and I suppose
what remains is EMMC boot as valid though I have not heard of any users
for this.
What is the test procedure for EMMC boot, can you explain and I will try
it on the Star64?
-E
