Add GPIO-based control for the PCIe Root Port PERST# signal. According to section 2.2 of the PCIe Electromechanical Specification (Revision 6.0), PERST# signal has to be deasserted after a delay of 100 ms (T_PVPERL) to ensure proper reset sequencing during PCIe initialization. Adapt to use the GPIO framework and make reset optional to keep DTB backward compatibility. Signed-off-by: Sai Krishna Musham <sai.krishna.musham@xxxxxxx> --- This patch depends on the following patch series. https://lore.kernel.org/all/20250217072713.635643-3-thippeswamy.havalige@xxxxxxx/ Changes for v3: - Use PCIE_T_PVPERL_MS define. Changes for v2: - Make the request GPIO optional. - Correct the reset sequence as per PERST# - Update commit message --- drivers/pci/controller/pcie-xilinx-cpm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index 81e8bfae53d0..558f1d602802 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -6,6 +6,8 @@ */ #include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/gpio/consumer.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqchip.h> @@ -568,8 +570,24 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct pci_host_bridge *bridge; struct resource_entry *bus; + struct gpio_desc *reset_gpio; int err; + /* Request the GPIO for PCIe reset signal */ + reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset_gpio)) { + dev_err(dev, "Failed to request reset GPIO\n"); + return PTR_ERR(reset_gpio); + } + + /* Assert the reset signal */ + gpiod_set_value(reset_gpio, 1); + + msleep(PCIE_T_PVPERL_MS); + + /* Deassert the reset signal */ + gpiod_set_value(reset_gpio, 0); + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port)); if (!bridge) return -ENODEV; -- 2.44.1
