On 25-02-24 15:06:19, Marcin Juszkiewicz wrote:
> > > > diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
> > > > new file mode 100644
> > > > index 000000000000..d98735f782e0
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/cix/sky1.dtsi
> > > > @@ -0,0 +1,264 @@
> > > > +// SPDX-License-Identifier: BSD-3-Clause
> > > > +/*
> > > > + * Copyright 2025 Cix Technology Group Co., Ltd.
> > > > + *
> > > > + */
> > > > +
> > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > >
> > > [..]
> > >
> > > > + arch_timer: timer {
> > > > + compatible = "arm,armv8-timer";
> > > > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > > > + clock-frequency = <1000000000>;
> > > > + interrupt-parent = <&gic>;
> > > > + arm,no-tick-in-suspend;
> > > > + };
> > >
> > > This is not Arm v8.0 SoC so where is non-secure EL2 virtual timer?
> >
> > It is the Arm v9 SoC and back compatible with Arm v8.
>
> Arm SoC has several timer interrupts:
>
> PPI 10: Non-secure EL2 physical timer interrupt
> PPI 11: Virtual timer interrupt
> PPI 12: Non-secure EL2 virtual timer
> PPI 13: Secure physical timer interrupt
> PPI 14: Non-secure physical timer interrupt
>
> You mention 10, 11, 13, 14 only like your SoC would be plain old Arm
> v8.0 one (Cortex-A53/A72).
>
> Sky1 (CP/CA/CS8180) is Arm v9 so should also list PPI 12 which came with
> VHE (Virtualization host extensions) which is mandatory for each Arm cpu
> v8.1 or above (and is implemented in A520/A720 cores).
Thanks for mentioning it. I will add PPI 12 for v2 patch set.
--
Best regards,
Peter
