[AMD Official Use Only - AMD Internal Distribution Only]
Hi Mani,
> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Sent: Monday, February 24, 2025 12:39 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige@xxxxxxx>
> Cc: bhelgaas@xxxxxxxxxx; lpieralisi@xxxxxxxxxx; kw@xxxxxxxxx;
> robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; linux-
> pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>; Gogada,
> Bharat Kumar <bharat.kumar.gogada@xxxxxxx>
> Subject: Re: [PATCH v3 2/2] PCI: xilinx-cpm: Add support for Versal Net
> CPM5NC Root Port controller
>
> On Mon, Feb 17, 2025 at 12:57:13PM +0530, Thippeswamy Havalige wrote:
> > The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> > incorporate the Coherency and PCIe Gen5 Module, specifically the
>
> What do you mean by 'Coherency' here? Cache coherency?
- Thank you for reviewing, Here Coherency is about CCIX/CXL but I don't
Think this should be mentioned here.
>
> > Next-Generation Compact Module (CPM5NC).
> >
> > The integrated CPM5NC block, along with the built-in bridge, can
> > function as a PCIe Root Port & supports the PCIe Gen5 protocol with
> > data transfer rates of up to 32 GT/s, capable of supporting up to a
> > x16 lane-width configuration.
> >
> > Bridge errors are managed using a specific interrupt line designed for
> > CPM5N. Intx interrupt support is not available.
>
> INTx
- Thanks for reviewing, I ll update this in next patch.
>
> >
> > Currently in this commit platform specific Bridge errors support is
> > not added.
> >
> > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx>
> > ---
> > Changes in v2:
> > - Update commit message.
> > ---
> > drivers/pci/controller/pcie-xilinx-cpm.c | 48
> > ++++++++++++++++--------
> > 1 file changed, 32 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c
> > b/drivers/pci/controller/pcie-xilinx-cpm.c
> > index 81e8bfae53d0..9b241c665f0a 100644
> > --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> > @@ -84,6 +84,7 @@ enum xilinx_cpm_version {
> > CPM,
> > CPM5,
> > CPM5_HOST1,
> > + CPM5NC_HOST,
> > };
> >
> > /**
> > @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct
> > xilinx_cpm_pcie *port) {
> > const struct xilinx_cpm_variant *variant = port->variant;
> >
> > + if (variant->version != CPM5NC_HOST)
> > + return;
> > +
> > if (cpm_pcie_link_up(port))
> > dev_info(port->dev, "PCIe Link is UP\n");
> > else
> > @@ -493,18 +497,16 @@ static void xilinx_cpm_pcie_init_port(struct
> xilinx_cpm_pcie *port)
> > XILINX_CPM_PCIE_REG_IDR);
> >
> > /*
> > - * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
> > - * CPM SLCR block.
> > + * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to CPM
> SLCR block.
>
> Spurious change.
- Thank you for reviewing. These comments were made in the v2 patch, and I have addressed them in this version.
Ll remove this changes in next patch.
>
> > */
> > writel(variant->ir_misc_value,
> > port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
> >
> > - if (variant->ir_enable) {
> > + if (variant->ir_enable)
> > writel(XILINX_CPM_PCIE_IR_LOCAL,
> > port->cpm_base + variant->ir_enable);
> > - }
>
> Same here. You should not do these kind of the cleanups in this patch as this
> patch is supposed to add only CPM5NC support.
- Thank you for reviewing. These comments were made in the v2 patch, and I have addressed them in this version.
Ll remove this changes in next patch.
> >
> > - /* Set Bridge enable bit */
> > + /* Set Bridge enable bit */
Thank you for reviewing. Ll update this in next patch.
>
> Same here.
>
> Rest LGTM!
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
