Hey folks, This patchset introduces clock driver support for Exynos 2200. It's modelled to take advantage of hwacg (hardware auto-clock gating). This means gates are not defined, so that hwacg takes care of the gating, which leads to a smaller and simpler clock driver design. Gate register definitions are left so that they're documented and in case a gate needs to be forcefully left open in the future, we won't have to define the register. Bindings have been tested appropriately: $ make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j4 dt_binding_check DT_SCHEMA_FILES="Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml" SCHEMA Documentation/devicetree/bindings/processed-schema.json Documentation/devicetree/bindings/iio/light/brcm,apds9160.yaml: ps-cancellation-current-picoamp: missing type definition CHKDT ./Documentation/devicetree/bindings LINT ./Documentation/devicetree/bindings DTEX Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.example.dts DTC [C] Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.example.dtb Best regards, Ivaylo Changes in v2: - unify binding and header name with compatible Ivaylo Ivanov (3): dt-bindings: clock: add Exynos2200 SoC clk: samsung: clk-pll: add support for pll_4311 clk: samsung: introduce Exynos2200 clock driver .../clock/samsung,exynos2200-cmu.yaml | 247 ++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos2200.c | 3928 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 1 + drivers/clk/samsung/clk-pll.h | 1 + .../clock/samsung,exynos2200-cmu.h | 431 ++ 6 files changed, 4609 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml create mode 100644 drivers/clk/samsung/clk-exynos2200.c create mode 100644 include/dt-bindings/clock/samsung,exynos2200-cmu.h -- 2.43.0
