On Thu, 20 Feb 2025 14:12:06 -0600 David Lechner <dlechner@xxxxxxxxxxxx> wrote: > On 2/20/25 7:54 AM, Antoniu Miclaus wrote: > > The AD4080 is a high-speed, low noise, low distortion, 20-bit, Easy > > Drive, successive approximation register (SAR) analog-to-digital > > converter (ADC). Maintaining high performance (signal-to-noise and > > distortion (SINAD) ratio > 90 dBFS) at signal frequencies in excess > > of 1 MHz enables the AD4080 to service a wide variety of precision, > > wide bandwidth data acquisition applications. Simplification of the > > input anti-alias filter design can be accomplished by applying over- > > sampling along with the integrated digital filtering and decimation to > > reduce noise and lower the output data rate for applications that do > > not require the lowest latency of the AD4080. > > > It looks like this was just copied from the datasheet, so not useful > at all for a cover letter. We can read it in the datasheet. > > Instead, please spend some time to explain the interesting and > unusual things about this driver that will help reviewers understand > *why* you are doing what you are doing. This is a very complex driver! > > In particular, on this one, the documentation on the FPGA IP block isn't > very detailed. So it will be very helpful to know more about how all of > the sync stuff is supposed to work and what kind of filtering is the > FPGA doing in addition to the filtering done in the ADC chip. > > > > This is a somewhat unusual device. I think a nice file with diagrams etc under Documentation would also be good to have! Jonathan
