On Tue, 18 Feb 2025 19:56:46 +0530, Jagadeesh Kona wrote:
> To configure the video PLLs and enable the video GDSCs on SM8450,
> SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along
> with MMCX. Therefore, update the videocc bindings to include
> the MXC power domain on these platforms.
>
> Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller")
> Signed-off-by: Jagadeesh Kona <quic_jkona@xxxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
