On 25-02-13 14:18:09, Stephan Gerhold wrote: > On Thu, Feb 13, 2025 at 02:44:02PM +0200, Abel Vesa wrote: > > On X Elite, there is a crypto engine IP block similar to ones found on > > SM8x50 platforms. > > > > Describe the crypto engine and its BAM. > > > > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> > > --- > > https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@xxxxxxxxxx/ > > --- > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > index 9d38436763432892ceef95daf0335d4cf446357c..5a2c5dd1dc2950b918af23c0939a112cbe47398b 100644 > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > @@ -3708,6 +3708,36 @@ pcie4_phy: phy@1c0e000 { > > status = "disabled"; > > }; > > > > + cryptobam: dma-controller@1dc4000 { > > + compatible = "qcom,bam-v1.7.0"; > > Hm, I would expect this is at least "qcom,bam-v1.7.4", "qcom,bam-v1.7.0" > given that this is a pretty recent SoC. I don't think this makes any > functional difference though, and we don't seem to have it on other > recent SoCs... Yep, will add both compatibles as suggested. > > > + reg = <0 0x01dc4000 0 0x28000>; > > + > > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > > + > > + #dma-cells = <1>; > > + > > + iommus = <&apps_smmu 0x480 0>, > > + <&apps_smmu 0x481 0>; > > Should be same as <&apps_smmu 0x480 0x1> (0x1 is applied as mask to the > SID, and 0x481 & ~0x1 = 0x480). Nope, the mask is on bit 16 through 31. That will result in different sid. > > > + > > + qcom,ee = <0>; > > + qcom,controlled-remotely; > > Please add "num-channels" and "qcom,num-ees". Otherwise you risk causing > crashes if the interconnect listed below isn't up (anymore) when the > driver probes the device. See: > https://lore.kernel.org/linux-arm-msm/20250213-x1e80100-crypto-v1-1-f93afdd4025a@xxxxxxxxxx/T/ Sure. Will do. This platform has 7 EEs and 30 channels according to documentation. > > > + }; > > + > > + crypto: crypto@1dfa000 { > > + compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; > > + reg = <0 0x01dfa000 0 0x6000>; > > + > > + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > > + interconnect-names = "memory"; > > + > > + dmas = <&cryptobam 4>, <&cryptobam 5>; > > + dma-names = "rx", "tx"; > > + > > + iommus = <&apps_smmu 0x480 0>, > > + <&apps_smmu 0x481 0>; > > <&apps_smmu 0x480 0x1>; See above. > > Thanks, > Stephan Thanks for reviewing. Abel
