On Feb 20, Bjorn Helgaas wrote: > On Sun, Feb 02, 2025 at 08:34:24PM +0100, Lorenzo Bianconi wrote: > > Configure PBus base address and address mask to allow the hw > > to detect if a given address is on PCIE0, PCIE1 or PCIE2. > > > > Signed-off-by: Lorenzo Bianconi <lorenzo@xxxxxxxxxx> > > --- > > drivers/pci/controller/pcie-mediatek-gen3.c | 30 ++++++++++++++++++++++++++++- > > 1 file changed, 29 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > > index aa24ac9aaecc749b53cfc4faf6399913d20cdbf2..9c2a592cae959de8fbe9ca5c5c2253f8eadf2c76 100644 > > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > > @@ -15,6 +15,7 @@ > > #include <linux/irqchip/chained_irq.h> > > #include <linux/irqdomain.h> > > #include <linux/kernel.h> > > +#include <linux/mfd/syscon.h> > > #include <linux/module.h> > > #include <linux/msi.h> > > #include <linux/of_device.h> > > @@ -24,6 +25,7 @@ > > #include <linux/platform_device.h> > > #include <linux/pm_domain.h> > > #include <linux/pm_runtime.h> > > +#include <linux/regmap.h> > > #include <linux/reset.h> > > > > #include "../pci.h" > > @@ -127,6 +129,13 @@ > > > > #define PCIE_MTK_RESET_TIME_US 10 > > > > +#define PCIE_EN7581_PBUS_ADDR(_n) (0x00 + ((_n) << 3)) > > +#define PCIE_EN7581_PBUS_ADDR_MASK(_n) (0x04 + ((_n) << 3)) > > +#define PCIE_EN7581_PBUS_BASE_ADDR(_n) \ > > + ((_n) == 2 ? 0x28000000 : \ > > + (_n) == 1 ? 0x24000000 : 0x20000000) > > Are these addresses something that should be expressed in devicetree? Do you have any example/pointer for it? > It seems unusual to encode addresses directly in a driver. AFAIK they are fixed for EN7581 SoC. Regards, Lorenzo > > Bjorn
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