On Wed, Feb 19, 2025 at 05:31:03PM +0800, Xu Yang wrote:
> Add USB2.0 controller and phy nodes.
>
> Signed-off-by: Xu Yang <xu.yang_2@xxxxxxx>
Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx95.dtsi | 30 ++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 0b64a1df3c7a..a7c87b9843bd 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -463,6 +463,13 @@ its: msi-controller@48040000 {
> };
> };
>
> + usbphynop: usbphynop {
> + compatible = "usb-nop-xceiv";
> + clocks = <&scmi_clk IMX95_CLK_HSIO>;
> + clock-names = "main_clk";
> + #phy-cells = <0>;
> + };
> +
> soc {
> compatible = "simple-bus";
> #address-cells = <2>;
> @@ -1579,6 +1586,29 @@ usb3_phy: phy@4c1f0040 {
> status = "disabled";
> };
>
> + usb2: usb@4c200000 {
> + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
> + reg = <0x0 0x4c200000 0x0 0x200>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_HSIO>,
> + <&scmi_clk IMX95_CLK_32K>;
> + clock-names = "usb_ctrl_root", "usb_wakeup";
> + iommus = <&smmu 0xf>;
> + phys = <&usbphynop>;
> + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> + fsl,usbmisc = <&usbmisc 0>;
> + status = "disabled";
> + };
> +
> + usbmisc: usbmisc@4c200200 {
> + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc",
> + "fsl,imx6q-usbmisc";
> + reg = <0x0 0x4c200200 0x0 0x200>,
> + <0x0 0x4c010014 0x0 0x04>;
> + #index-cells = <1>;
> + };
> +
> pcie0: pcie@4c300000 {
> compatible = "fsl,imx95-pcie";
> reg = <0 0x4c300000 0 0x10000>,
> --
> 2.34.1
>
