On 2025/2/19 05:51, Stephen Boyd wrote: > Quoting Xukai Wang (2025-02-17 06:45:16) >> +$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Canaan Kendryte K230 Clock >> + >> +maintainers: >> + - Xukai Wang <kingxukai@xxxxxxxxxxxx> > Is this missing a description of the device? Alright. Here's the added description: The K230 clock controller manages the PLLs and system clocks (sysclk), generating clocks for different domains. The internal PLLs are derived from the external osc24M, and all sysclk signals use either the PLLs' dividers or directly the osc24M source. Not all macros defined in include/dt-bindings/clock/canaan,k230-clk.h are available for use in clock consumer nodes yet. Does this looks appropriate? >> + reg = <0x91102000 0x1000>, > Is there a reason why the PLL range comes first? As I thought that the PLL is the base for other system clocks (sysclk), so I placed it first. > What's at 0x91101000? More clk hardware? Regarding 0x91101000, there is no clk hardware at that address; it is related to the Reset Management Unit (RMU). You can refer to the K230 Technical Reference Manual [1] on page 11 for its Address Space mapping. Thanks for your time. Link: https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf [1] >> + <0x91100000 0x1000>;
