Hi, >> The top level interrupt may be different and APM specific unless other >> vendors adapt the same bit definitions. I highly doubt other vendor >> will use the same bit definitions. The CSW is APM only. The MCB A, MCB >> B, and memory controller are APM only. The L3, and SoC are APM specify >> only. For L1 and L2, I will need to check with the CPU designer - but >> likely APM specific. > > So it sounds to me like this whole driver will control APM-specific hw > so a single driver should be fine. Okay... But I would like Rob agrees on the DT binding before I generate this new patch. Rob, can you comment on the DT binding in previous email thread? -Loc -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
