On Thu, Apr 30, 2015 at 1:07 PM, Fabio Estevam <festevam@xxxxxxxxx> wrote:
> Hi Frank,
>
> On Wed, Apr 29, 2015 at 11:20 AM, <Frank.Li@xxxxxxxxxxxxx> wrote:
>
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0>;
>> + operating-points = <
>> + /* KHz uV */
>> + 996000 1075000
>> + 792000 975000
>> + >;
>> + clock-latency = <61036>; /* two CLK32 periods */
>> + clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
>> + <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
>> + clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main";
>> + };
>> + };
>
> That's a dual core, so you also need to pass cpu1 ;-)
SMP is not enabled yet.
cpu1 will be added when enable SMP.
I am working on that.
best regards
Frank Li
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