From: Niravkumar L Rabara <niravkumar.l.rabara@xxxxxxxxx>
The Agilex5 devkit supports a separate TB daughter board.
This board includes a SPI EEPROM and different LED pin configuration
compared to the default daughter board for the Agilex5 devkit.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@xxxxxxxxx>
---
arch/arm64/boot/dts/intel/Makefile | 1 +
.../dts/intel/socfpga_agilex5_socdk_tb.dts | 27 +++++++++++++++++++
2 files changed, 28 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tb.dts
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index d39cfb723f5b..4c977b0aaf9b 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_agilex5_socdk.dtb \
+ socfpga_agilex5_socdk_tb.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tb.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tb.dts
new file mode 100644
index 000000000000..3cda73e12f38
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tb.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025, Altera Corporation
+ */
+#include "socfpga_agilex5_socdk.dts"
+
+/ {
+ model = "SoCFPGA Agilex5 SoCDK - TB";
+ compatible = "intel,socfpga-agilex5-socdk-tb", "intel,socfpga-agilex5";
+
+ leds {
+ led-0 {
+ label = "hps_led0";
+ gpios = <&portb 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ spidev@0{
+ compatible = "rohm,dh2228fv";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
--
2.25.1
