Now that bus clock support has been implemented into the Broadcom Kona
clock driver, add bus clocks corresponding to HUB_TIMER, SDIO, UART and
BSC, as well as the USB OTG bus clock.
Signed-off-by: Artur Weber <aweber.kernel@xxxxxxxxx>
---
drivers/clk/bcm/clk-bcm21664.c | 107 +++++++++++++++++++++++++++++++----
include/dt-bindings/clock/bcm21664.h | 19 ++++++-
2 files changed, 111 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/bcm/clk-bcm21664.c b/drivers/clk/bcm/clk-bcm21664.c
index 520c3aeb4ea9c4a431512c0909f9545c1761d17a..c9d15bde1d49c345c160880f72c96aea94dd9f55 100644
--- a/drivers/clk/bcm/clk-bcm21664.c
+++ b/drivers/clk/bcm/clk-bcm21664.c
@@ -39,6 +39,11 @@ static struct peri_clk_data hub_timer_data = {
.trig = TRIGGER(0x0a40, 4),
};
+static struct bus_clk_data hub_timer_apb_data = {
+ .gate = HW_SW_GATE(0x0414, 18, 3, 2),
+ .hyst = HYST(0x0414, 10, 11),
+};
+
static struct ccu_data aon_ccu_data = {
BCM21664_CCU_COMMON(aon, AON),
.policy = {
@@ -47,7 +52,9 @@ static struct ccu_data aon_ccu_data = {
},
.kona_clks = {
[BCM21664_AON_CCU_HUB_TIMER] =
- KONA_CLK(aon, hub_timer, peri),
+ KONA_CLK_PREREQ(aon, hub_timer, peri, hub_timer_apb),
+ [BCM21664_AON_CCU_HUB_TIMER_APB] =
+ KONA_CLK(aon, hub_timer_apb, bus),
[BCM21664_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
},
};
@@ -122,6 +129,26 @@ static struct peri_clk_data sdio4_sleep_data = {
.gate = HW_SW_GATE(0x0360, 18, 2, 3),
};
+static struct bus_clk_data sdio1_ahb_data = {
+ .gate = HW_SW_GATE(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+ .gate = HW_SW_GATE(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+ .gate = HW_SW_GATE(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+ .gate = HW_SW_GATE(0x0360, 16, 0, 1),
+};
+
+static struct bus_clk_data usb_otg_ahb_data = {
+ .gate = HW_SW_GATE(0x0348, 16, 0, 1),
+};
+
static struct ccu_data master_ccu_data = {
BCM21664_CCU_COMMON(master, MASTER),
.policy = {
@@ -130,13 +157,13 @@ static struct ccu_data master_ccu_data = {
},
.kona_clks = {
[BCM21664_MASTER_CCU_SDIO1] =
- KONA_CLK(master, sdio1, peri),
+ KONA_CLK_PREREQ(master, sdio1, peri, sdio1_ahb),
[BCM21664_MASTER_CCU_SDIO2] =
- KONA_CLK(master, sdio2, peri),
+ KONA_CLK_PREREQ(master, sdio2, peri, sdio2_ahb),
[BCM21664_MASTER_CCU_SDIO3] =
- KONA_CLK(master, sdio3, peri),
+ KONA_CLK_PREREQ(master, sdio3, peri, sdio3_ahb),
[BCM21664_MASTER_CCU_SDIO4] =
- KONA_CLK(master, sdio4, peri),
+ KONA_CLK_PREREQ(master, sdio4, peri, sdio4_ahb),
[BCM21664_MASTER_CCU_SDIO1_SLEEP] =
KONA_CLK(master, sdio1_sleep, peri),
[BCM21664_MASTER_CCU_SDIO2_SLEEP] =
@@ -145,6 +172,16 @@ static struct ccu_data master_ccu_data = {
KONA_CLK(master, sdio3_sleep, peri),
[BCM21664_MASTER_CCU_SDIO4_SLEEP] =
KONA_CLK(master, sdio4_sleep, peri),
+ [BCM21664_MASTER_CCU_SDIO1_AHB] =
+ KONA_CLK(master, sdio1_ahb, bus),
+ [BCM21664_MASTER_CCU_SDIO2_AHB] =
+ KONA_CLK(master, sdio2_ahb, bus),
+ [BCM21664_MASTER_CCU_SDIO3_AHB] =
+ KONA_CLK(master, sdio3_ahb, bus),
+ [BCM21664_MASTER_CCU_SDIO4_AHB] =
+ KONA_CLK(master, sdio4_ahb, bus),
+ [BCM21664_MASTER_CCU_USB_OTG_AHB] =
+ KONA_CLK(master, usb_otg_ahb, bus),
[BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
},
};
@@ -225,6 +262,38 @@ static struct peri_clk_data bsc4_data = {
.trig = TRIGGER(0x0afc, 19),
};
+static struct bus_clk_data uartb_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0400, 16, 0, 1),
+};
+
+static struct bus_clk_data uartb2_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0404, 16, 0, 1),
+};
+
+static struct bus_clk_data uartb3_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0408, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc1_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+ .hyst = HYST(0x0458, 8, 9),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+ .hyst = HYST(0x045c, 8, 9),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0470, 16, 0, 1),
+ .hyst = HYST(0x0470, 8, 9),
+};
+
+static struct bus_clk_data bsc4_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0474, 16, 0, 1),
+ .hyst = HYST(0x0474, 8, 9),
+};
+
static struct ccu_data slave_ccu_data = {
BCM21664_CCU_COMMON(slave, SLAVE),
.policy = {
@@ -233,19 +302,33 @@ static struct ccu_data slave_ccu_data = {
},
.kona_clks = {
[BCM21664_SLAVE_CCU_UARTB] =
- KONA_CLK(slave, uartb, peri),
+ KONA_CLK_PREREQ(slave, uartb, peri, uartb_apb),
[BCM21664_SLAVE_CCU_UARTB2] =
- KONA_CLK(slave, uartb2, peri),
+ KONA_CLK_PREREQ(slave, uartb2, peri, uartb2_apb),
[BCM21664_SLAVE_CCU_UARTB3] =
- KONA_CLK(slave, uartb3, peri),
+ KONA_CLK_PREREQ(slave, uartb3, peri, uartb3_apb),
[BCM21664_SLAVE_CCU_BSC1] =
- KONA_CLK(slave, bsc1, peri),
+ KONA_CLK_PREREQ(slave, bsc1, peri, bsc1_apb),
[BCM21664_SLAVE_CCU_BSC2] =
- KONA_CLK(slave, bsc2, peri),
+ KONA_CLK_PREREQ(slave, bsc2, peri, bsc2_apb),
[BCM21664_SLAVE_CCU_BSC3] =
- KONA_CLK(slave, bsc3, peri),
+ KONA_CLK_PREREQ(slave, bsc3, peri, bsc3_apb),
[BCM21664_SLAVE_CCU_BSC4] =
- KONA_CLK(slave, bsc4, peri),
+ KONA_CLK_PREREQ(slave, bsc4, peri, bsc4_apb),
+ [BCM21664_SLAVE_CCU_UARTB_APB] =
+ KONA_CLK(slave, uartb_apb, bus),
+ [BCM21664_SLAVE_CCU_UARTB2_APB] =
+ KONA_CLK(slave, uartb2_apb, bus),
+ [BCM21664_SLAVE_CCU_UARTB3_APB] =
+ KONA_CLK(slave, uartb3_apb, bus),
+ [BCM21664_SLAVE_CCU_BSC1_APB] =
+ KONA_CLK(slave, bsc1_apb, bus),
+ [BCM21664_SLAVE_CCU_BSC2_APB] =
+ KONA_CLK(slave, bsc2_apb, bus),
+ [BCM21664_SLAVE_CCU_BSC3_APB] =
+ KONA_CLK(slave, bsc3_apb, bus),
+ [BCM21664_SLAVE_CCU_BSC4_APB] =
+ KONA_CLK(slave, bsc4_apb, bus),
[BCM21664_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
},
};
diff --git a/include/dt-bindings/clock/bcm21664.h b/include/dt-bindings/clock/bcm21664.h
index 7c7492742f3d4ca439236f2f352e432989409570..8d3e3796c72b02eace84dfb90d6264dee0297a33 100644
--- a/include/dt-bindings/clock/bcm21664.h
+++ b/include/dt-bindings/clock/bcm21664.h
@@ -26,7 +26,8 @@
/* aon CCU clock ids */
#define BCM21664_AON_CCU_HUB_TIMER 0
-#define BCM21664_AON_CCU_CLOCK_COUNT 1
+#define BCM21664_AON_CCU_HUB_TIMER_APB 1
+#define BCM21664_AON_CCU_CLOCK_COUNT 2
/* master CCU clock ids */
@@ -38,7 +39,12 @@
#define BCM21664_MASTER_CCU_SDIO2_SLEEP 5
#define BCM21664_MASTER_CCU_SDIO3_SLEEP 6
#define BCM21664_MASTER_CCU_SDIO4_SLEEP 7
-#define BCM21664_MASTER_CCU_CLOCK_COUNT 8
+#define BCM21664_MASTER_CCU_SDIO1_AHB 8
+#define BCM21664_MASTER_CCU_SDIO2_AHB 9
+#define BCM21664_MASTER_CCU_SDIO3_AHB 10
+#define BCM21664_MASTER_CCU_SDIO4_AHB 11
+#define BCM21664_MASTER_CCU_USB_OTG_AHB 12
+#define BCM21664_MASTER_CCU_CLOCK_COUNT 13
/* slave CCU clock ids */
@@ -49,6 +55,13 @@
#define BCM21664_SLAVE_CCU_BSC2 4
#define BCM21664_SLAVE_CCU_BSC3 5
#define BCM21664_SLAVE_CCU_BSC4 6
-#define BCM21664_SLAVE_CCU_CLOCK_COUNT 7
+#define BCM21664_SLAVE_CCU_BSC1_APB 7
+#define BCM21664_SLAVE_CCU_BSC2_APB 8
+#define BCM21664_SLAVE_CCU_BSC3_APB 9
+#define BCM21664_SLAVE_CCU_BSC4_APB 10
+#define BCM21664_SLAVE_CCU_UARTB_APB 11
+#define BCM21664_SLAVE_CCU_UARTB2_APB 12
+#define BCM21664_SLAVE_CCU_UARTB3_APB 13
+#define BCM21664_SLAVE_CCU_CLOCK_COUNT 14
#endif /* _CLOCK_BCM21664_H */
--
2.48.1
