On Fri, Feb 14, 2025 at 8:56 PM Andre Przywara <andre.przywara@xxxxxxx> wrote: > > The PRCM CCU in the A523 SoC contains some clocks that only feature a > P (shift) factor, but no M divider. > Treat this as a special case of an MP clock: by forcing the M mask to be > 0 bits wide, this always result in the M divider value to be 1. > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> Reviewed-by: Chen-Yu Tsai <wens@xxxxxxxx>
