On Fri, Feb 14, 2025 at 04:57:42PM +0100, Maud Spierings via B4 Relay wrote: > From: Maud Spierings <maudspierings@xxxxxxxxxxxxxx> > > Currently to configure each IOMUXC_SW_PAD_CTL_PAD the raw value of this > register is written in the dts, these values are not obvious. Add defines > which describe the fields of this register which can be or-ed together to > produce readable settings. > > Signed-off-by: Maud Spierings <maudspierings@xxxxxxxxxxxxxx> > --- > arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 27 ++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h > index b1f11098d248ed5fc8ac42daed808beebe3bf7bc..b231d5968d07d1e135963b714c3fe80ddd8641ab 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h > +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h > @@ -6,6 +6,33 @@ > #ifndef __DTS_IMX8MM_PINFUNC_H > #define __DTS_IMX8MM_PINFUNC_H > > +//Drive Strength > +#define MX8MM_DSE_X1 0x0 > +#define MX8MM_DSE_X2 0x4 > +#define MX8MM_DSE_X4 0x2 > +#define MX8MM_DSE_X6 0x6 > + > +//Slew Rate > +#define MX8MM_FSEL_FAST 0x10 > +#define MX8MM_FSEL_SLOW 0x0 > + > +//Open Drain > +#define MX8MM_ODE_ENABLE 0x20 > +#define MX8MM_ODE_DISABLE 0x0 > + > +#define MX8MM_PULL_DOWN 0x0 > +#define MX8MM_PULL_UP 0x40 > + > +//Hysteresis > +#define MX8MM_HYS_CMOS 0x0 > +#define MX8MM_HYS_SCHMITT 0x80 > + > +#define MX8MM_PULL_ENABLE 0x100 > +#define MX8MM_PULL_DISABLE 0x0 > + > +//? > +#define MX8MM_MYSTERY_BIT 0x40000000 Suppose it is SION See pinctrl driver's IMX_PAD_SION Frank > + > /* > * The pin function ID is a tuple of > * <mux_reg conf_reg input_reg mux_mode input_val> > > -- > 2.48.1 > >
