On 2/13/25 10:02, Krzysztof Kozlowski wrote:
On Mon, Feb 10, 2025 at 04:21:02PM +0100, Amelie Delaunay wrote:From: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx> STM32MP21 family is composed of 3 SoCs defined as following: -STM32MP211: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP213: STM32MP211 + a second ETH, CAN-FD. -STM32MP215: STM32MP213 + Display and CSI2. A second diversity layer exists for security features/ A35 frequency: -STM32MP21xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx> Signed-off-by: Amelie Delaunay <amelie.delaunay@xxxxxxxxxxx> --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 130 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp213.dtsi | 9 +++ arch/arm64/boot/dts/st/stm32mp215.dtsi | 9 +++ arch/arm64/boot/dts/st/stm32mp21xc.dtsi | 8 ++ arch/arm64/boot/dts/st/stm32mp21xf.dtsi | 8 ++ 5 files changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d384359e0ea16e2593795ff48d4a699324c8ca75 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx> for STMicroelectronics. + */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + status = "disabled"; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@4ac00000 {MMIO nodes belong to the soc.
Indeed.
+ compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + arm,no-tick-in-suspend; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <2>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x0 0x80000000>;ranges is the second property. See DTS coding style.
Ok.
+ dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>; + + rifsc: bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <2>; + ranges;and here is third.+ dma-ranges; + + usart2: serial@400e0000 {Although addresses seem wrong. How bus could start at 0x4208 but device at 0x400e?+ compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x0 0x400>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon";Which soc is this? DTSI says stm32mp211, commit STM32MP21, but compatible xxx25?
Looks like a new compatible is needed, and I guess it is also true for stm32mp231.
+ reg = <0x44230000 0x0 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp213.dtsi b/arch/arm64/boot/dts/st/stm32mp213.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..22cdedd9abbf4efac2334d497618daa6cc76727b --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp213.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx> for STMicroelectronics. + */ +#include "stm32mp211.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp215.dtsi b/arch/arm64/boot/dts/st/stm32mp215.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d2c63e92b3cc15ec64898374fd2e745a9c71eb6d --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp215.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx> for STMicroelectronics. + */ +#include "stm32mp213.dtsi" + +/ { +};What is the point of this file exactly?
Skeleton file for upcoming second ethernet and can-fd peripherals, not available on stm32mp211.
diff --git a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..39507a7564c8488647a3276eb227eb5f446359e6 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx> for STMicroelectronics. + */ + +/ { +};And this and others.
Skeleton file for upcoming cryptographic support, not available on stm32mp21xa and stm32mp21xd.
As said previously, same split is used on other STM32 MPUs. Regards, Amelie
